What is the significance of co-planarity in die bonding?
At the recent IMAPS Conference in Arizona, co-planarity in die bonding was a key topic due to its importance in 2.5 and 3D chip stacking. Ensuring co-planar surfaces is crucial for the performance of vertically integrated devices, as it affects pad/pillar contact. Optimizing planarity involves specific variables, especially in die stacking and copper pillar processes where bonding surfaces must be co-planar.
Bonding without parallelism compensation
For many applications, a fixed tool and chuck are sufficient for co-planarity. This approach relies on mechanical systems and provides excellent co-planarity. There is no need for adjustments, resulting in higher stability, repeatability, and accuracy—but there is no ability to actively adjust.
Bonding with active parallelism compensation
Active parallel compensation requires actuators which can be prone to error. The accuracy of gap measurement and actuator resolution affects the outcome. This method can be costly and requires sub-micron precision.
Bonding with passive parallelism compensation
Components align with the substrate or a reference surface, enabling free tool movement. When placing a die on the substrate or stacking chips, the placement tool adjusts position across to ensure co-planarity, assuming the chip and die are relatively flat (>0.5mm).
Vertically integrated devices are becoming more common as we seek to add more functions within limited space, such as in cell phones. Die-to-die interconnects and multichip modules will continue to advance these technologies.
MRSI focuses on accuracy and precision in assembly solutions. Contact us to learn more about our die bonding, active alignment and fluid dispensing solutions.